diff options
| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2020-06-01 20:30:58 +0300 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2020-06-04 21:11:56 +0300 |
| commit | 19aefbc778b8b8e87c2d31be9736c634f0ea95a8 (patch) | |
| tree | 2d5d29329515bde0864e2575fea7c1e8830c4385 /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | b8226d62e77620d372f6eb8c34b51798f3962414 (diff) | |
| download | linux-19aefbc778b8b8e87c2d31be9736c634f0ea95a8.tar.xz | |
drm/i915: Fix wrong CDCLK adjustment changes
Previous patch didn't take into account all pipes
but only those in state, which could cause wrong
CDCLK conclcusions and calculations.
Also there was a severe issue with min_cdclk being
assigned to 0 every compare cycle.
Too bad this was found by me only after merge.
This could be also causing the issues in test, however
not clear - anyway marking this as fixing the
"Adjust CDCLK accordingly to our DBuf bw needs".
v2: - s/pipe/crtc->pipe/
- save a bit of instructions by
skipping inactive pipes, without
getting 0 DBuf slice mask for it.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200601173058.5084-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f9b0fc7317de..08468b121d02 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) { struct intel_atomic_state *state = cdclk_state->base.state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_bw_state *bw_state = NULL; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int min_cdclk, i; + enum pipe pipe; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) if (min_cdclk < 0) return min_cdclk; + bw_state = intel_atomic_get_bw_state(state); + if (IS_ERR(bw_state)) + return PTR_ERR(bw_state); + if (cdclk_state->min_cdclk[i] == min_cdclk) continue; @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) } min_cdclk = cdclk_state->force_min_cdclk; + for_each_pipe(dev_priv, pipe) { + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_bw_state *bw_state; - - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); - - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + if (!bw_state) + continue; min_cdclk = max(bw_state->min_cdclk, min_cdclk); } |