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| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2020-02-07 20:37:41 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-02-24 10:34:35 +0300 |
| commit | 2130de7d5e1ab1d5725b2e2c923fb6238a471131 (patch) | |
| tree | 78ef458a3a2c067944f8023859b55dc57b9a6a57 /drivers/gpu/drm/gma500 | |
| parent | 9c270ce33da574a3738cc19376e7e5fdb223d7df (diff) | |
| download | linux-2130de7d5e1ab1d5725b2e2c923fb6238a471131.tar.xz | |
KVM: nVMX: Use correct root level for nested EPT shadow page tables
[ Upstream commit 148d735eb55d32848c3379e460ce365f2c1cbe4b ]
Hardcode the EPT page-walk level for L2 to be 4 levels, as KVM's MMU
currently also hardcodes the page walk level for nested EPT to be 4
levels. The L2 guest is all but guaranteed to soft hang on its first
instruction when L1 is using EPT, as KVM will construct 4-level page
tables and then tell hardware to use 5-level page tables.
Fixes: 855feb673640 ("KVM: MMU: Add 5 level EPT & Shadow page table support.")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/gma500')
0 files changed, 0 insertions, 0 deletions