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authorInki Dae <inki.dae@samsung.com>2013-07-24 10:44:30 +0400
committerInki Dae <inki.dae@samsung.com>2013-09-05 08:43:42 +0400
commitb10d6350a5dfce9c4640e0974936452afd171a13 (patch)
tree9320a0572d6ffd873168fa2c12b7362e5a63c8ea /drivers/gpu/drm/exynos/exynos_drm_g2d.c
parenta1bfacf4006a3bb410b0fa85e203f9249d2d35e9 (diff)
downloadlinux-b10d6350a5dfce9c4640e0974936452afd171a13.tar.xz
drm/exynos: add runtime pm interfaces to g2d driver
This patch makes g2d power domain and clock to be controlled through pm runtime interfaces instead of controlling them respectively. Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_g2d.c')
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_g2d.c40
1 files changed, 28 insertions, 12 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index eddea4941483..b31356e67e5e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -808,17 +808,8 @@ static void g2d_dma_start(struct g2d_data *g2d,
int ret;
ret = pm_runtime_get_sync(g2d->dev);
- if (ret < 0) {
- dev_warn(g2d->dev, "failed pm power on.\n");
- return;
- }
-
- ret = clk_prepare_enable(g2d->gate_clk);
- if (ret < 0) {
- dev_warn(g2d->dev, "failed to enable clock.\n");
- pm_runtime_put_sync(g2d->dev);
+ if (ret < 0)
return;
- }
writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
@@ -871,7 +862,6 @@ static void g2d_runqueue_worker(struct work_struct *work)
runqueue_work);
mutex_lock(&g2d->runqueue_mutex);
- clk_disable_unprepare(g2d->gate_clk);
pm_runtime_put_sync(g2d->dev);
complete(&g2d->runqueue_node->complete);
@@ -1524,7 +1514,33 @@ static int g2d_resume(struct device *dev)
}
#endif
-static SIMPLE_DEV_PM_OPS(g2d_pm_ops, g2d_suspend, g2d_resume);
+#ifdef CONFIG_PM_RUNTIME
+static int g2d_runtime_suspend(struct device *dev)
+{
+ struct g2d_data *g2d = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(g2d->gate_clk);
+
+ return 0;
+}
+
+static int g2d_runtime_resume(struct device *dev)
+{
+ struct g2d_data *g2d = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(g2d->gate_clk);
+ if (ret < 0)
+ dev_warn(dev, "failed to enable clock.\n");
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops g2d_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume)
+ SET_RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL)
+};
#ifdef CONFIG_OF
static const struct of_device_id exynos_g2d_match[] = {