diff options
author | Otto Pflüger <otto.pflueger@abscue.de> | 2023-07-24 09:56:53 +0300 |
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committer | Noralf Trønnes <noralf@tronnes.org> | 2023-08-02 14:18:07 +0300 |
commit | 8cc8ccbaa5d89b65a32f0260b0cd2288d2c9b6dc (patch) | |
tree | 02179c3cc499b92f0aab81412628704415a5c0a3 /drivers/gpu/drm/drm_mipi_dbi.c | |
parent | 8e4bb53c902ed2b06a2c4778e6dbb2c1eeec4960 (diff) | |
download | linux-8cc8ccbaa5d89b65a32f0260b0cd2288d2c9b6dc.tar.xz |
drm/mipi-dbi: Lock SPI bus before setting D/C GPIO
Multiple displays may be connected to the same bus and share a D/C GPIO,
so the display driver needs exclusive access to the bus to ensure that
it can control the D/C GPIO safely.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: David Lechner <david@lechnology.com>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230724065654.5269-2-otto.pflueger@abscue.de
Diffstat (limited to 'drivers/gpu/drm/drm_mipi_dbi.c')
-rw-r--r-- | drivers/gpu/drm/drm_mipi_dbi.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index c871d9f096b8..e90f0bf895b3 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -1140,10 +1140,13 @@ static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd, return -ENOMEM; tr[1].rx_buf = buf; + + spi_bus_lock(spi->controller); gpiod_set_value_cansleep(dbi->dc, 0); spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr)); - ret = spi_sync(spi, &m); + ret = spi_sync_locked(spi, &m); + spi_bus_unlock(spi->controller); if (ret) goto err_free; @@ -1177,19 +1180,24 @@ static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd, MIPI_DBI_DEBUG_COMMAND(*cmd, par, num); + spi_bus_lock(spi->controller); gpiod_set_value_cansleep(dbi->dc, 0); speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1); ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1); + spi_bus_unlock(spi->controller); if (ret || !num) return ret; if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes) bpw = 16; + spi_bus_lock(spi->controller); gpiod_set_value_cansleep(dbi->dc, 1); speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); + ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); + spi_bus_unlock(spi->controller); - return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num); + return ret; } /** @@ -1271,7 +1279,8 @@ EXPORT_SYMBOL(mipi_dbi_spi_init); * @len: Buffer length * * This SPI transfer helper breaks up the transfer of @buf into chunks which - * the SPI controller driver can handle. + * the SPI controller driver can handle. The SPI bus must be locked when + * calling this. * * Returns: * Zero on success, negative error code on failure. @@ -1305,7 +1314,7 @@ int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz, buf += chunk; len -= chunk; - ret = spi_sync(spi, &m); + ret = spi_sync_locked(spi, &m); if (ret) return ret; } |