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author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-12-18 12:35:04 +0300 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-12-18 16:00:17 +0300 |
commit | 81ff52b705775433a955b2746d37b87bdc89a3d0 (patch) | |
tree | 38fa940f2bd55bcb546c8dc3a199ee7de57c38aa /drivers/gpu/drm/drm_atomic_state_helper.c | |
parent | da42104f589d979bbe402703fd836cec60befae1 (diff) | |
download | linux-81ff52b705775433a955b2746d37b87bdc89a3d0.tar.xz |
drm/i915/gt: Ratelimit display power w/a
For very light workloads that frequently park, acquiring the display
power well (required to prevent the dmc from trashing the system) takes
longer than the execution. A good example is the igt_coherency selftest,
which is slowed down by an order of magnitude in the worst case with
powerwell cycling. To prevent frequent cycling, while keeping our fast
soft-rc6, use a timer to delay release of the display powerwell.
Fixes: 311770173fac ("drm/i915/gt: Schedule request retirement when timeline idles")
References: https://gitlab.freedesktop.org/drm/intel/issues/848
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191218093504.3477048-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/drm_atomic_state_helper.c')
0 files changed, 0 insertions, 0 deletions