diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-07-15 20:11:25 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-10-01 16:33:27 +0300 |
| commit | 9099ea19ca8ad21ab7f2a7abc06e270adeb8b02f (patch) | |
| tree | d1834ed3d9ee165dc2cac44df5cf66e72db22e57 /drivers/gpu/drm/armada/armada_crtc.c | |
| parent | 583268035825fc5ef0bbc467631fea0358831cbe (diff) | |
| download | linux-9099ea19ca8ad21ab7f2a7abc06e270adeb8b02f.tar.xz | |
drm/armada: move write to dma_ctrl0 to armada_drm_crtc_plane_disable()
Move the write to clear the DMA enable bit, and augment it with clearing
the graphics enable bit for the primary plane.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/gpu/drm/armada/armada_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/armada/armada_crtc.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 007fc5d3eb54..89decc5bdcd4 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -703,7 +703,7 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, struct drm_plane *plane) { - u32 sram_para1; + u32 sram_para1, dma_ctrl0_mask; /* * Drop our reference on any framebuffer attached to this plane. @@ -719,9 +719,17 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; /* Power down most RAMs and FIFOs if this is the primary plane */ - if (plane->type == DRM_PLANE_TYPE_PRIMARY) + if (plane->type == DRM_PLANE_TYPE_PRIMARY) { sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66; + dma_ctrl0_mask = CFG_GRA_ENA; + } else { + dma_ctrl0_mask = CFG_DMA_ENA; + } + + spin_lock_irq(&dcrtc->irq_lock); + armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); + spin_unlock_irq(&dcrtc->irq_lock); armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); } |