diff options
| author | George Shen <George.Shen@amd.com> | 2021-12-09 04:28:14 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-12-30 16:54:44 +0300 |
| commit | 0d988e5de7aa5ee8865cbc664180ae67918a6b19 (patch) | |
| tree | 52a49a9a6bcd9798afa109a12a19057fae1adebf /drivers/gpu/drm/amd/display | |
| parent | 3db817fce43ec3d423b969911151dd849f4d7351 (diff) | |
| download | linux-0d988e5de7aa5ee8865cbc664180ae67918a6b19.tar.xz | |
drm/amd/display: Remove CR AUX RD Interval limit for LTTPR
[Why]
DP spec specifies that DPRX shall use the read interval in the
TRAINING_AUX_RD_INTERVAL_PHY_REPEATER LTTPR DPCD register. This
register's bit definition is the same as the AUX read interval register
for DPRX.
[How}
Remove logic which forces AUX read interval to 100us for repeaters when
in LTTPR non-transparent mode.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 04878817e622..9dc99929b0cd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1544,9 +1544,6 @@ static enum link_training_result perform_clock_recovery_sequence( /* 3. wait receiver to lock-on*/ wait_time_microsec = lt_settings->cr_pattern_time; - if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) - wait_time_microsec = TRAINING_AUX_RD_INTERVAL; - if (link->dc->debug.apply_vendor_specific_lttpr_wa && (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) { wait_time_microsec = 16000; |