summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display
diff options
context:
space:
mode:
authorDave Airlie <airlied@redhat.com>2017-11-02 22:32:08 +0300
committerDave Airlie <airlied@redhat.com>2017-11-02 22:32:08 +0300
commit26c860d5579684528114c3875ef88f7796330eb5 (patch)
treefbc71d3e54f0c823a6032727a303a47ffe1fe8b6 /drivers/gpu/drm/amd/display
parentaf9111336071ee9378e1db70ac8f4c2b7fcd17a1 (diff)
parent1f3493faa8d73b0332d46ea79448b10b66fb1af0 (diff)
downloadlinux-26c860d5579684528114c3875ef88f7796330eb5.tar.xz
Merge branch 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few fixes for DC for 4.15. * 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu/display: fix integer arithmetic problem drm/amdgpu/display: remove unused REG_OFFSET macro drm/amdgpu/display: provide ASSERT macros unconditionally drm/amd/display: Read resource_straps from registers for DCE12 drm/amd: Add DCE12 resource strap registers drm/amd/display: Explicitly call ->reset for each object drm/amd/display: Use single fail label in init_drm_dev drm/amd/display: Use plane pointer to avoid line breaks drm/amd/display: fix null pointer dereference amdgpu/dc: Avoid dereferencing NULL pointer drm/amd/display: Don't print error when bo_pin is interrupted drm/amd/display: Use constants from atom.h for HDMI caps read drm/amd/display: check if modeset is required before adding plane drm/amd/display: fix high part address in dm_plane_helper_prepare_fb() drm/amd/display : add high part address calculation for underlay drm/amd/display: Fix no display on Fiji Revert "drm/amd/display: Match actual state during S3 resume."
Diffstat (limited to 'drivers/gpu/drm/amd/display')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c116
-rw-r--r--drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c6
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_stream.c2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c19
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c19
-rw-r--r--drivers/gpu/drm/amd/display/dc/dm_services.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/os_types.h4
8 files changed, 83 insertions, 88 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d0ee1b3b8b5c..33a15a1d818c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -641,11 +641,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
struct drm_connector *connector;
struct drm_crtc *crtc;
struct drm_crtc_state *new_crtc_state;
- struct dm_crtc_state *dm_crtc_state;
- struct drm_plane *plane;
- struct drm_plane_state *plane_state;
- struct dm_plane_state *dm_plane_state;
- struct dm_atomic_state *cached_state;
int ret = 0;
int i;
@@ -684,34 +679,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
new_crtc_state->active_changed = true;
- cached_state = to_dm_atomic_state(adev->dm.cached_state);
-
- /*
- * During suspend, the cached state is saved before all streams are
- * disabled. Refresh cached state to match actual current state before
- * restoring it.
- */
- WARN_ON(kref_read(&cached_state->context->refcount) > 1);
- dc_release_state(cached_state->context);
-
- for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
- dm_crtc_state = to_dm_crtc_state(new_crtc_state);
- if (dm_crtc_state->stream) {
- WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1);
- dc_stream_release(dm_crtc_state->stream);
- dm_crtc_state->stream = NULL;
- }
- }
-
- for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) {
- dm_plane_state = to_dm_plane_state(plane_state);
- if (dm_plane_state->dc_state) {
- WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1);
- dc_plane_state_release(dm_plane_state->dc_state);
- dm_plane_state->dc_state = NULL;
- }
- }
-
ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
drm_atomic_state_put(adev->dm.cached_state);
@@ -1361,13 +1328,16 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
for (i = 0; i < dm->dc->caps.max_planes; i++) {
- mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
- GFP_KERNEL);
- if (!mode_info->planes[i]) {
+ struct amdgpu_plane *plane;
+
+ plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
+ mode_info->planes[i] = plane;
+
+ if (!plane) {
DRM_ERROR("KMS: Failed to allocate plane\n");
- goto fail_free_planes;
+ goto fail;
}
- mode_info->planes[i]->base.type = mode_info->plane_type[i];
+ plane->base.type = mode_info->plane_type[i];
/*
* HACK: IGT tests expect that each plane can only have one
@@ -1381,14 +1351,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
DRM_ERROR("KMS: Failed to initialize plane\n");
- goto fail_free_planes;
+ goto fail;
}
}
for (i = 0; i < dm->dc->caps.max_streams; i++)
if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
DRM_ERROR("KMS: Failed to initialize crtc\n");
- goto fail_free_planes;
+ goto fail;
}
dm->display_indexes_num = dm->dc->caps.max_streams;
@@ -1405,20 +1375,20 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
if (!aconnector)
- goto fail_free_planes;
+ goto fail;
aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
if (!aencoder)
- goto fail_free_connector;
+ goto fail;
if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
DRM_ERROR("KMS: Failed to initialize encoder\n");
- goto fail_free_encoder;
+ goto fail;
}
if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
DRM_ERROR("KMS: Failed to initialize connector\n");
- goto fail_free_encoder;
+ goto fail;
}
if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
@@ -1443,14 +1413,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case CHIP_VEGA10:
if (dce110_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
- goto fail_free_encoder;
+ goto fail;
}
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
- goto fail_free_encoder;
+ goto fail;
}
/*
* Temporary disable until pplib/smu interaction is implemented
@@ -1460,17 +1430,13 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
- goto fail_free_encoder;
+ goto fail;
}
- drm_mode_config_reset(dm->ddev);
-
return 0;
-fail_free_encoder:
+fail:
kfree(aencoder);
-fail_free_connector:
kfree(aconnector);
-fail_free_planes:
for (i = 0; i < dm->dc->caps.max_planes; i++)
kfree(mode_info->planes[i]);
return -1;
@@ -1804,6 +1770,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
{
uint64_t tiling_flags;
uint64_t fb_location = 0;
+ uint64_t chroma_addr = 0;
unsigned int awidth;
const struct drm_framebuffer *fb = &amdgpu_fb->base;
int ret = 0;
@@ -1866,9 +1833,13 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
plane_state->address.video_progressive.luma_addr.low_part
= lower_32_bits(fb_location);
+ plane_state->address.video_progressive.luma_addr.high_part
+ = upper_32_bits(fb_location);
+ chroma_addr = fb_location + (u64)(awidth * fb->height);
plane_state->address.video_progressive.chroma_addr.low_part
- = lower_32_bits(fb_location) +
- (awidth * fb->height);
+ = lower_32_bits(chroma_addr);
+ plane_state->address.video_progressive.chroma_addr.high_part
+ = upper_32_bits(chroma_addr);
plane_state->plane_size.video.luma_size.x = 0;
plane_state->plane_size.video.luma_size.y = 0;
plane_state->plane_size.video.luma_size.width = awidth;
@@ -2924,6 +2895,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
struct amdgpu_framebuffer *afb;
struct drm_gem_object *obj;
struct amdgpu_bo *rbo;
+ uint64_t chroma_addr = 0;
int r;
struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
unsigned int awidth;
@@ -2950,7 +2922,8 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
amdgpu_bo_unreserve(rbo);
if (unlikely(r != 0)) {
- DRM_ERROR("Failed to pin framebuffer\n");
+ if (r != -ERESTARTSYS)
+ DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
return r;
}
@@ -2965,11 +2938,16 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
} else {
awidth = ALIGN(new_state->fb->width, 64);
+ plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
plane_state->address.video_progressive.luma_addr.low_part
= lower_32_bits(afb->address);
+ plane_state->address.video_progressive.luma_addr.high_part
+ = upper_32_bits(afb->address);
+ chroma_addr = afb->address + (u64)(awidth * new_state->fb->height);
plane_state->address.video_progressive.chroma_addr.low_part
- = lower_32_bits(afb->address) +
- (awidth * new_state->fb->height);
+ = lower_32_bits(chroma_addr);
+ plane_state->address.video_progressive.chroma_addr.high_part
+ = upper_32_bits(chroma_addr);
}
}
@@ -3101,6 +3079,11 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
+ /* Create (reset) the plane state */
+ if (aplane->base.funcs->reset)
+ aplane->base.funcs->reset(&aplane->base);
+
+
return res;
}
@@ -3136,6 +3119,10 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
+ /* Create (reset) the plane state */
+ if (acrtc->base.funcs->reset)
+ acrtc->base.funcs->reset(&acrtc->base);
+
acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
@@ -3488,6 +3475,9 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
&aconnector->base,
&amdgpu_dm_connector_helper_funcs);
+ if (aconnector->base.funcs->reset)
+ aconnector->base.funcs->reset(&aconnector->base);
+
amdgpu_dm_connector_init_helper(
dm,
aconnector,
@@ -3874,8 +3864,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
/* update planes when needed */
for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
struct drm_crtc *crtc = new_plane_state->crtc;
- struct drm_crtc_state *new_crtc_state =
- drm_atomic_get_new_crtc_state(state, crtc);
+ struct drm_crtc_state *new_crtc_state;
struct drm_framebuffer *fb = new_plane_state->fb;
bool pflip_needed;
struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
@@ -3885,7 +3874,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
continue;
}
- if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
+ if (!fb || !crtc || pcrtc != crtc)
+ continue;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ if (!new_crtc_state->active)
continue;
pflip_needed = !state->allow_modeset;
@@ -4675,6 +4668,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
} else {
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+ continue;
+
if (!new_crtc_state->enable)
continue;
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 15cbfc400633..4f8a95368ffc 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -531,7 +531,7 @@ static void calculate_bandwidth(
}
switch (data->lb_bpc[i]) {
case 8:
- data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
+ data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
break;
case 10:
data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c47da645d3b8..e70612eaf257 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -24,6 +24,7 @@
*/
#include "dm_services.h"
+#include "atom.h"
#include "dm_helpers.h"
#include "dc.h"
#include "grph_object_id.h"
@@ -45,7 +46,6 @@
#include "dce/dce_11_0_enum.h"
#include "dce/dce_11_0_sh_mask.h"
-#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C /* Copied from atombios.h */
#define LINK_INFO(...) \
dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
__VA_ARGS__)
@@ -1696,7 +1696,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
- if (masked_chip_caps == (0x2 << 2)) {
+ if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
/* DP159, Retimer settings */
eng_id = pipe_ctx->stream_res.stream_enc->id;
@@ -1707,7 +1707,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
write_i2c_default_retimer_setting(pipe_ctx,
is_vga_mode, is_over_340mhz);
}
- } else if (masked_chip_caps == (0x1 << 2)) {
+ } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
/* PI3EQX1204, Redriver settings */
write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 5cf69af9693d..572b885195c7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -288,7 +288,7 @@ bool dc_stream_set_cursor_position(
pos_cpy.enable = false;
- if (ipp->funcs->ipp_cursor_set_position != NULL)
+ if (ipp !=NULL && ipp->funcs->ipp_cursor_set_position != NULL)
ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
if (mi != NULL && mi->funcs->set_cursor_position != NULL)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2a6d3ca12954..399a5984ada3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1370,16 +1370,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
- /* mst support - use total stream count */
- if (pipe_ctx->plane_res.mi != NULL) {
- pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
- pipe_ctx->plane_res.mi,
- stream->timing.h_total,
- stream->timing.v_total,
- stream->timing.pix_clk_khz,
- context->stream_count);
- }
-
pipe_ctx->stream->sink->link->psr_enabled = false;
return DC_OK;
@@ -2891,6 +2881,15 @@ static void dce110_apply_ctx_for_surface(
if (pipe_ctx->stream != stream)
continue;
+ /* Need to allocate mem before program front end for Fiji */
+ if (pipe_ctx->plane_res.mi != NULL)
+ pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
+ pipe_ctx->plane_res.mi,
+ pipe_ctx->stream->timing.h_total,
+ pipe_ctx->stream->timing.v_total,
+ pipe_ctx->stream->timing.pix_clk_khz,
+ context->stream_count);
+
dce110_program_front_end_for_pipe(dc, pipe_ctx);
program_surface_visibility(dc, pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 3ed28a870e20..5c48c22d9d98 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -501,12 +501,19 @@ static void read_dce_straps(
struct dc_context *ctx,
struct resource_straps *straps)
{
- /* TODO: Registers are missing */
- /*REG_GET_2(CC_DC_HDMI_STRAPS,
- HDMI_DISABLE, &straps->hdmi_disable,
- AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-
- REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/
+ uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
+
+ straps->audio_stream_number = get_reg_field_value(reg_val,
+ CC_DC_MISC_STRAPS,
+ AUDIO_STREAM_NUMBER);
+ straps->hdmi_disable = get_reg_field_value(reg_val,
+ CC_DC_MISC_STRAPS,
+ HDMI_DISABLE);
+
+ reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
+ straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
+ DC_PINSTRAPS,
+ DC_PINSTRAPS_AUDIO);
}
static struct audio *create_audio(
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index c8190c38a644..d4917037ac42 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -160,9 +160,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx,
/* These macros need to be used with soc15 registers in order to retrieve
* the actual offset.
*/
-#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX])
-#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX])
-
#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 86170b40b5c5..a87c0329541f 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -61,8 +61,6 @@
* general debug capabilities
*
*/
-#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
-
#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
#define ASSERT_CRITICAL(expr) do { \
if (WARN_ON(!(expr))) { \
@@ -86,8 +84,6 @@
#define BREAK_TO_DEBUGGER() ASSERT(0)
-#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
-
#define DC_ERR(...) do { \
dm_error(__VA_ARGS__); \
BREAK_TO_DEBUGGER(); \