diff options
author | Maxime Ripard <mripard@kernel.org> | 2019-10-03 17:38:50 +0300 |
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committer | Maxime Ripard <mripard@kernel.org> | 2019-10-03 17:38:50 +0300 |
commit | 4092de1ba34eb376791809fb366bc15f8a9e0b7c (patch) | |
tree | 6262d4dfcfa7ff9eda8e8d1d0a711711fcae8785 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | |
parent | a00d17e0a71ae2e4fdaac46e1c12785d3346c3f2 (diff) | |
parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) | |
download | linux-4092de1ba34eb376791809fb366bc15f8a9e0b7c.tar.xz |
Merge drm/drm-next into drm-misc-next
We haven't done any backmerge for a while due to the merge window, and it
starts to become an issue for komeda. Let's bring 5.4-rc1 in.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 40 |
1 files changed, 26 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c index 240749e4cf83..5a188b2bc033 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c @@ -233,14 +233,14 @@ static void mpc2_ogam_get_reg_field( reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; } -static void mpc20_power_on_ogam_lut( +void mpc20_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on) { struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, - MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1); + MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0); } @@ -368,6 +368,11 @@ void apply_DEDCN20_305_wa( { struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); + if (mpc->ctx->dc->debug.cm_in_bypass) { + REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); + return; + } + if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) { /*hw fixed in new review*/ return; @@ -390,10 +395,16 @@ void mpc2_set_output_gamma( enum dc_lut_mode next_mode; struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); + if (mpc->ctx->dc->debug.cm_in_bypass) { + REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); + return; + } + if (params == NULL) { REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); return; } + current_mode = mpc20_get_ogam_current(mpc, mpcc_id); if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) next_mode = LUT_RAM_B; @@ -435,23 +446,22 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) { struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled; - REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled); - - if (mpc_disabled) { - ASSERT(0); - return; - } REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); - if (top_sel == 0xf) { - REG_GET_2(MPCC_STATUS[mpcc_id], - MPCC_BUSY, &mpc_busy, - MPCC_IDLE, &mpc_idle); + REG_GET_3(MPCC_STATUS[mpcc_id], + MPCC_BUSY, &mpc_busy, + MPCC_IDLE, &mpc_idle, + MPCC_DISABLED, &mpc_disabled); - ASSERT(mpc_busy == 0); - ASSERT(mpc_idle == 1); + if (top_sel == 0xf) { + ASSERT(!mpc_busy); + ASSERT(mpc_idle); + ASSERT(mpc_disabled); + } else { + ASSERT(!mpc_disabled); + ASSERT(!mpc_idle); } } @@ -488,6 +498,7 @@ const struct mpc_funcs dcn20_mpc_funcs = { .insert_plane = mpc1_insert_plane, .remove_mpcc = mpc1_remove_mpcc, .mpc_init = mpc1_mpc_init, + .mpc_init_single_inst = mpc1_mpc_init_single_inst, .update_blending = mpc2_update_blending, .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp, .wait_for_idle = mpc2_assert_idle_mpcc, @@ -498,6 +509,7 @@ const struct mpc_funcs dcn20_mpc_funcs = { .set_output_csc = mpc2_set_output_csc, .set_ocsc_default = mpc2_set_ocsc_default, .set_output_gamma = mpc2_set_output_gamma, + .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, }; void dcn20_mpc_construct(struct dcn20_mpc *mpc20, |