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authorEric Badger <ebadger@purestorage.com>2021-10-10 20:06:56 +0300
committerTony Luck <tony.luck@intel.com>2021-10-11 18:28:46 +0300
commit537bddd069c743759addf422d0b8f028ff0f8dbc (patch)
tree6d62627119d692a5568e29654dbcd5e02484abe9 /drivers/edac
parent0b6d4ab2165c46c7f236744a2d05264f40172ae9 (diff)
downloadlinux-537bddd069c743759addf422d0b8f028ff0f8dbc.tar.xz
EDAC/sb_edac: Fix top-of-high-memory value for Broadwell/Haswell
The computation of TOHM is off by one bit. This missed bit results in too low a value for TOHM, which can cause errors in regular memory to incorrectly report: EDAC MC0: 1 CE Error at MMIOH area, on addr 0x000000207fffa680 on any memory Fixes: 50d1bb93672f ("sb_edac: add support for Haswell based systems") Cc: stable@vger.kernel.org Reported-by: Meeta Saggi <msaggi@purestorage.com> Signed-off-by: Eric Badger <ebadger@purestorage.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20211010170127.848113-1-ebadger@purestorage.com
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/sb_edac.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 4c626fcd4dcb..1522d4aa2ca6 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -1052,7 +1052,7 @@ static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
rc = ((reg << 6) | rc) << 26;
- return rc | 0x1ffffff;
+ return rc | 0x3ffffff;
}
static u64 knl_get_tolm(struct sbridge_pvt *pvt)