diff options
| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2010-02-03 17:44:12 +0300 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-08 03:40:24 +0300 |
| commit | 623b4ac4bf9e767991c66e29b47dd4b19458fb42 (patch) | |
| tree | 9cf9c5ef8ac1ab714a35db1baf627fb701a98287 /drivers/dma/shdma.c | |
| parent | fc4618575f79eea062cdc51715040e40cd35b71c (diff) | |
| download | linux-623b4ac4bf9e767991c66e29b47dd4b19458fb42.tar.xz | |
sh: fix Transfer Size calculation in both DMA drivers
Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers
do not take into account bits 3:2 of the Transfer Size field in the CHCR
register, besides, bit-field defines set bit 2, but the mask only passes bits
1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all
these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to
be fixed too.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/dma/shdma.c')
| -rw-r--r-- | drivers/dma/shdma.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index 427c3effc432..3e1037c5ebd1 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c @@ -105,10 +105,14 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) return false; /* waiting */ } +static unsigned int ts_shift[] = TS_SHIFT; static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan) { u32 chcr = sh_dmae_readl(sh_chan, CHCR); - return ts_shift[(chcr & CHCR_TS_MASK) >> CHCR_TS_SHIFT]; + int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) | + ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT); + + return ts_shift[cnt]; } static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |