Merge tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we have couple of new drivers along with updates to drivers:

   - new drivers for the DesignWare AXI DMAC and MediaTek High-Speed DMA
     controllers

   - stm32 dma and qcom bam dma driver updates

   - norandom test option for dmatest"

* tag 'dmaengine-4.17-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (30 commits)
  dmaengine: stm32-dma: properly mask irq bits
  dmaengine: stm32-dma: fix max items per transfer
  dmaengine: stm32-dma: fix DMA IRQ status handling
  dmaengine: stm32-dma: Improve memory burst management
  dmaengine: stm32-dma: fix typo and reported checkpatch warnings
  dmaengine: stm32-dma: fix incomplete configuration in cyclic mode
  dmaengine: stm32-dma: threshold manages with bitfield feature
  dt-bindings: stm32-dma: introduce DMA features bitfield
  dt-bindings: rcar-dmac: Document r8a77470 support
  dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacks
  dmaengine: dw-axi-dmac: fix spelling mistake: "catched" -> "caught"
  dmaengine: edma: Check the memory allocation for the memcpy dma device
  dmaengine: at_xdmac: fix rare residue corruption
  dmaengine: mediatek: update MAINTAINERS entry with MediaTek DMA driver
  dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC
  dt-bindings: dmaengine: Add MediaTek High-Speed DMA controller bindings
  dt-bindings: Document the Synopsys DW AXI DMA bindings
  dmaengine: Introduce DW AXI DMAC driver
  dmaengine: pl330: fix a race condition in case of threaded irqs
  dmaengine: imx-sdma: fix pagefault when channel is disabled during interrupt
  ...

1 files changed, 21 insertions, 0 deletions

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index e7db24c67030..ccd03c3cedfe 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -338,6 +338,7 @@ struct sdma_channel {
 	unsigned int			chn_real_count;
 	struct tasklet_struct		tasklet;
 	struct imx_dma_data		data;
+	bool				enabled;
 };
 
 #define IMX_DMA_SG_LOOP		BIT(0)
@@ -596,7 +597,14 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
 
 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 {
+	unsigned long flags;
+	struct sdma_channel *sdmac = &sdma->channel[channel];
+
 	writel(BIT(channel), sdma->regs + SDMA_H_START);
+
+	spin_lock_irqsave(&sdmac->lock, flags);
+	sdmac->enabled = true;
+	spin_unlock_irqrestore(&sdmac->lock, flags);
 }
 
 /*
@@ -685,6 +693,14 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 	struct sdma_buffer_descriptor *bd;
 	int error = 0;
 	enum dma_status	old_status = sdmac->status;
+	unsigned long flags;
+
+	spin_lock_irqsave(&sdmac->lock, flags);
+	if (!sdmac->enabled) {
+		spin_unlock_irqrestore(&sdmac->lock, flags);
+		return;
+	}
+	spin_unlock_irqrestore(&sdmac->lock, flags);
 
 	/*
 	 * loop mode. Iterate over descriptors, re-setup them and
@@ -938,10 +954,15 @@ static int sdma_disable_channel(struct dma_chan *chan)
 	struct sdma_channel *sdmac = to_sdma_chan(chan);
 	struct sdma_engine *sdma = sdmac->sdma;
 	int channel = sdmac->channel;
+	unsigned long flags;
 
 	writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 	sdmac->status = DMA_ERROR;
 
+	spin_lock_irqsave(&sdmac->lock, flags);
+	sdmac->enabled = false;
+	spin_unlock_irqrestore(&sdmac->lock, flags);
+
 	return 0;
 }