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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-03-18 15:26:31 +0300
committerVinod Koul <vinod.koul@intel.com>2016-04-04 19:41:43 +0300
commit080edf75d337d35faa6fc3df99342b10d2848d16 (patch)
tree122bebcd8b7caebd967f1ceb3ec373d2d950fb23 /drivers/dma/hsu
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
downloadlinux-080edf75d337d35faa6fc3df99342b10d2848d16.tar.xz
dmaengine: hsu: set HSU_CH_MTSR to memory width
HSU_CH_MTSR register should be programmed to a minimum size to transfer. This size on a memory side of the transfer. Program it accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/hsu')
-rw-r--r--drivers/dma/hsu/hsu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c
index eef145edb936..c7643e022578 100644
--- a/drivers/dma/hsu/hsu.c
+++ b/drivers/dma/hsu/hsu.c
@@ -64,10 +64,10 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
if (hsuc->direction == DMA_MEM_TO_DEV) {
bsr = config->dst_maxburst;
- mtsr = config->dst_addr_width;
+ mtsr = config->src_addr_width;
} else if (hsuc->direction == DMA_DEV_TO_MEM) {
bsr = config->src_maxburst;
- mtsr = config->src_addr_width;
+ mtsr = config->dst_addr_width;
}
hsu_chan_disable(hsuc);