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authorDan Williams <dan.j.williams@intel.com>2022-05-27 20:57:01 +0300
committerDan Williams <dan.j.williams@intel.com>2022-07-22 03:19:24 +0300
commit1b58b4cac6fc6fab55f34f74087594125fc60b84 (patch)
tree6b6685df5d82ea9e32c130945e23c2d91982b27a /drivers/cxl/acpi.c
parentde516b40116e98c60ee475e92108453686098c85 (diff)
downloadlinux-1b58b4cac6fc6fab55f34f74087594125fc60b84.tar.xz
cxl/port: Record parent dport when adding ports
At the time that cxl_port instances are being created, cache the dport from the parent port that points to this new child port. This will be useful for region provisioning when walking the tree to calculate decoder targets, and saves rewalking the dport list after the fact to build this information. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220624041950.559155-1-dan.j.williams@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/acpi.c')
-rw-r--r--drivers/cxl/acpi.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 8f021241699f..64004eb672d0 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -211,8 +211,7 @@ static int add_host_bridge_uport(struct device *match, void *arg)
if (rc)
return rc;
- port = devm_cxl_add_port(host, match, dport->component_reg_phys,
- root_port);
+ port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);
if (IS_ERR(port))
return PTR_ERR(port);
dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));