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| author | Kim Phillips <kim.phillips@freescale.com> | 2011-11-21 12:13:27 +0400 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2011-11-21 12:21:51 +0400 |
| commit | c3e337f88a5b3784cb3c806ffd650d06adff1ea5 (patch) | |
| tree | 12ca78132c4ccc74257bf2ad634e1c06a062d2bd /drivers/crypto/talitos.h | |
| parent | ad42d5fc85383278663ecb58a24f6547ad0ba735 (diff) | |
| download | linux-c3e337f88a5b3784cb3c806ffd650d06adff1ea5.tar.xz | |
crypto: talitos - support for channel remap and 2nd IRQ
Some later SEC v3.x are equipped with a second IRQ line.
By correctly assigning IRQ affinity, this feature can be
used to increase performance on dual core parts, like the
MPC8572E and P2020E.
The existence of the 2nd IRQ is determined from the device
node's interrupt property. If present, the driver remaps
two of four channels, which in turn makes those channels
trigger their interrupts on the 2nd line instead of the first.
To handle single- and dual-IRQ combinations efficiently,
talitos gets two new interrupt handlers and back-half workers.
[includes a fix to MCR_LO's address.]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/talitos.h')
| -rw-r--r-- | drivers/crypto/talitos.h | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h index 3ed319da853c..3c173954ef29 100644 --- a/drivers/crypto/talitos.h +++ b/drivers/crypto/talitos.h @@ -34,16 +34,24 @@ /* global register offset addresses */ #define TALITOS_MCR 0x1030 /* master control register */ -#define TALITOS_MCR_LO 0x1038 +#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */ +#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */ +#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */ +#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */ #define TALITOS_MCR_SWR 0x1 /* s/w reset */ +#define TALITOS_MCR_LO 0x1034 #define TALITOS_IMR 0x1008 /* interrupt mask register */ #define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */ #define TALITOS_IMR_DONE 0x00055 /* done IRQs */ #define TALITOS_IMR_LO 0x100C #define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */ #define TALITOS_ISR 0x1010 /* interrupt status register */ -#define TALITOS_ISR_CHERR 0xaa /* channel errors mask */ -#define TALITOS_ISR_CHDONE 0x55 /* channel done mask */ +#define TALITOS_ISR_4CHERR 0xaa /* 4 channel errors mask */ +#define TALITOS_ISR_4CHDONE 0x55 /* 4 channel done mask */ +#define TALITOS_ISR_CH_0_2_ERR 0x22 /* channels 0, 2 errors mask */ +#define TALITOS_ISR_CH_0_2_DONE 0x11 /* channels 0, 2 done mask */ +#define TALITOS_ISR_CH_1_3_ERR 0x88 /* channels 1, 3 errors mask */ +#define TALITOS_ISR_CH_1_3_DONE 0x44 /* channels 1, 3 done mask */ #define TALITOS_ISR_LO 0x1014 #define TALITOS_ICR 0x1018 /* interrupt clear register */ #define TALITOS_ICR_LO 0x101C |