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| author | Billy Tsai <billy_tsai@aspeedtech.com> | 2022-02-21 04:27:05 +0300 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-03-02 16:38:29 +0300 |
| commit | 571426631acf46e2999c7ecd1e9d048172969a43 (patch) | |
| tree | 8ed89adf6c7d0b98413c9e04f1f3ec524f97bae5 /drivers/crypto/mxs-dcp.c | |
| parent | 6270bf1f0197739a9cddaf0a40699a99b7357cb5 (diff) | |
| download | linux-571426631acf46e2999c7ecd1e9d048172969a43.tar.xz | |
iio: adc: aspeed: Add divider flag to fix incorrect voltage reading.
The formula for the ADC sampling period in ast2400/ast2500 is:
ADC clock period = PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0])
When ADC0C[9:0] is set to 0 the sampling voltage will be lower than
expected, because the hardware may not have enough time to
charge/discharge to a stable voltage. This patch use the flag
CLK_DIVIDER_ONE_BASED which will use the raw value read from the
register, with the value of zero considered invalid to conform to the
corrected formula.
Fixes: 573803234e72 ("iio: Aspeed ADC")
Reported-by: Konstantin Klubnichkin <kitsok@yandex-team.ru>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220221012705.22008-1-billy_tsai@aspeedtech.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/crypto/mxs-dcp.c')
0 files changed, 0 insertions, 0 deletions