diff options
| author | Srujana Challa <schalla@marvell.com> | 2021-01-15 16:52:22 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-01-22 06:58:03 +0300 |
| commit | 43ac0b824f1cb7c63c5fe98ea2b80ec480412601 (patch) | |
| tree | 2081b7bc1caf3a0fa2e963a394993b6afcff966b /drivers/crypto/marvell/octeontx2/otx2_cptpf.h | |
| parent | fe16eceab0463c160a333b7df4edd707f3a24d5c (diff) | |
| download | linux-43ac0b824f1cb7c63c5fe98ea2b80ec480412601.tar.xz | |
crypto: octeontx2 - load microcode and create engine groups
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for AEs), and configures
all engines.
Signed-off-by: Suheil Chandran <schandran@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/marvell/octeontx2/otx2_cptpf.h')
| -rw-r--r-- | drivers/crypto/marvell/octeontx2/otx2_cptpf.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf.h b/drivers/crypto/marvell/octeontx2/otx2_cptpf.h index 8a9805f89fee..ac9795978286 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf.h @@ -6,6 +6,7 @@ #define __OTX2_CPTPF_H #include "otx2_cpt_common.h" +#include "otx2_cptpf_ucode.h" struct otx2_cptpf_dev; struct otx2_cptvf_info { @@ -27,6 +28,8 @@ struct otx2_cptpf_dev { void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */ struct pci_dev *pdev; /* PCI device handle */ struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM]; + struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */ + /* AF <=> PF mbox */ struct otx2_mbox afpf_mbox; struct work_struct afpf_mbox_work; |