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authorKai Ye <yekai13@huawei.com>2021-11-20 07:47:36 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2021-11-26 08:25:17 +0300
commit376a5c3cdd7cf47d2436dd466548c0fff792f4c7 (patch)
tree6ce8b41023d8f91eecab69fde719c33a2ff01408 /drivers/crypto/hisilicon/sec2/sec_main.c
parentd3b04a4398fe8022c9ca4b5ac6ab08059334b180 (diff)
downloadlinux-376a5c3cdd7cf47d2436dd466548c0fff792f4c7.tar.xz
crypto: hisilicon - modify the value of engine type rate
Modify the value of type rate from new QM spec. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/hisilicon/sec2/sec_main.c')
-rw-r--r--drivers/crypto/hisilicon/sec2/sec_main.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 90551bf38b52..26d3ab1d308b 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -105,7 +105,7 @@
#define SEC_SQE_MASK_OFFSET 64
#define SEC_SQE_MASK_LEN 48
-#define SEC_SHAPER_TYPE_RATE 128
+#define SEC_SHAPER_TYPE_RATE 400
struct sec_hw_error {
u32 int_msk;