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| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-06-13 14:31:38 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-06-27 17:18:13 +0300 |
| commit | 8d1336c241bdadf61a56e398d82d1e512dbff5f8 (patch) | |
| tree | e7f06bd2b5380fa69e5340e6ea21bd527b0570cc /drivers/crypto/cavium/cpt/cptvf_mbox.c | |
| parent | 63d3cd297bc045536e4c3eaddc2cf6aa4a8cf0df (diff) | |
| download | linux-8d1336c241bdadf61a56e398d82d1e512dbff5f8.tar.xz | |
mtd: spi-nor: cadence-quadspi: add reset control
Get the reset control properties for the QSPI controller and bring them
out of reset. Most will have just one reset bit, but there is an additional
OCP reset bit that is used ECC. The OCP reset bit will also need to get
de-asserted as well. [1]
The reason this patch is needed is in the case where a bootloader leaves
the QSPI controller in a reset state, or a state where init cannot occur
successfully, the patch will put the QSPI controller into a clean state.
[1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html
Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
[tudor.ambarus@microchip.com: declare rstc and rstc_ocp on the same line]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/crypto/cavium/cpt/cptvf_mbox.c')
0 files changed, 0 insertions, 0 deletions