diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-03 23:32:21 +0300 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-03 23:32:21 +0300 |
commit | 8226f11318bd03ae0dbf028f7c433071cf4927f4 (patch) | |
tree | e8799beee4a5985a75b41763ef2093f10e4887b0 /drivers/cpufreq | |
parent | e8f4abf8fd1a2beb94983cb95ed713df75b3d135 (diff) | |
parent | 9bd0bd264578fe191bf5d2ff23f9887b91862536 (diff) | |
download | linux-8226f11318bd03ae0dbf028f7c433071cf4927f4.tar.xz |
Merge tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- added support for MIPSr5 and P5600 cores
- converted Loongson PCI driver into a PCI host driver using the
generic PCI framework
- added emulation of CPUCFG command for Loogonson64 cpus
- removed of LASAT, PMC MSP71xx and NEC MARKEINS/EMMA
- ioremap cleanup
- fix for a race between two threads faulting the same page
- various cleanups and fixes
* tag 'mips_5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (143 commits)
MIPS: ralink: drop ralink_clk_init for mt7621
MIPS: ralink: bootrom: mark a function as __init to save some memory
MIPS: Loongson64: Reorder CPUCFG model match arms
MIPS: Expose Loongson CPUCFG availability via HWCAP
MIPS: Loongson64: Guard against future cores without CPUCFG
MIPS: Fix build warning about "PTR_STR" redefinition
MIPS: Loongson64: Remove not used pci.c
MIPS: Loongson64: Define PCI_IOBASE
MIPS: CPU_LOONGSON2EF need software to maintain cache consistency
MIPS: DTS: Fix build errors used with various configs
MIPS: Loongson64: select NO_EXCEPT_FILL
MIPS: Fix IRQ tracing when call handle_fpe() and handle_msa_fpe()
MIPS: mm: add page valid judgement in function pte_modify
mm/memory.c: Add memory read privilege on page fault handling
mm/memory.c: Update local TLB if PTE entry exists
MIPS: Do not flush tlb page when updating PTE entry
MIPS: ingenic: Default to a generic board
MIPS: ingenic: Add support for GCW Zero prototype
MIPS: ingenic: DTS: Add memory info of GCW Zero
MIPS: Loongson64: Switch to generic PCI driver
...
Diffstat (limited to 'drivers/cpufreq')
-rw-r--r-- | drivers/cpufreq/loongson2_cpufreq.c | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c index 909f40fbcde2..d05e761d9572 100644 --- a/drivers/cpufreq/loongson2_cpufreq.c +++ b/drivers/cpufreq/loongson2_cpufreq.c @@ -20,7 +20,6 @@ #include <linux/delay.h> #include <linux/platform_device.h> -#include <asm/clock.h> #include <asm/idle.h> #include <asm/mach-loongson2ef/loongson.h> @@ -58,29 +57,20 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy, loongson2_clockmod_table[index].driver_data) / 8; /* setting the cpu frequency */ - clk_set_rate(policy->clk, freq * 1000); + loongson2_cpu_set_rate(freq); return 0; } static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) { - struct clk *cpuclk; int i; unsigned long rate; int ret; - cpuclk = clk_get(NULL, "cpu_clk"); - if (IS_ERR(cpuclk)) { - pr_err("couldn't get CPU clk\n"); - return PTR_ERR(cpuclk); - } - rate = cpu_clock_freq / 1000; - if (!rate) { - clk_put(cpuclk); + if (!rate) return -EINVAL; - } /* clock table init */ for (i = 2; @@ -88,20 +78,16 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) i++) loongson2_clockmod_table[i].frequency = (rate * i) / 8; - ret = clk_set_rate(cpuclk, rate * 1000); - if (ret) { - clk_put(cpuclk); + ret = loongson2_cpu_set_rate(rate); + if (ret) return ret; - } - policy->clk = cpuclk; cpufreq_generic_init(policy, &loongson2_clockmod_table[0], 0); return 0; } static int loongson2_cpufreq_exit(struct cpufreq_policy *policy) { - clk_put(policy->clk); return 0; } |