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| author | Olof Johansson <olof@lixom.net> | 2018-12-31 22:54:03 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2018-12-31 22:54:03 +0300 |
| commit | cac1fc8fb561ac766468394d49c3dd11a2b8cb44 (patch) | |
| tree | 5483f72b13b766cfbd6f025d2a828fef3d1d0203 /drivers/cpufreq/imx6q-cpufreq.c | |
| parent | bd3fde386decf09317ff4a07cd0d05380a22f525 (diff) | |
| parent | 54518ed45734bb7ebf2773b1d32120c62338cc93 (diff) | |
| download | linux-cac1fc8fb561ac766468394d49c3dd11a2b8cb44.tar.xz | |
Merge branch 'fixes' into next/soc
Merge in fixes here, since the last batch didn't make it in before the
release of 4.20, and we might as well group them with this set of
patches.
* fixes: (822 commits)
arm64: dts: renesas: draak: Fix CVBS input
ARM: dts: Fix OMAP4430 SDP Ethernet startup
ARM: dts: am335x-pdu001: Fix polarity of card detection input
ARM: OMAP1: ams-delta: Fix audio permanently muted
ARM: dts: omap5: Fix dual-role mode on Super-Speed port
arm64: dts: rockchip: fix rk3399-rockpro64 regulator gpios
ARM: dts: imx7d-nitrogen7: Fix the description of the Wifi clock
ARM: imx: update the cpu power up timing setting on i.mx6sx
Revert "arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K"
ARM: dts: imx7d-pico: Describe the Wifi clock
ARM: dts: realview: Fix some more duplicate regulator nodes
MAINTAINERS: update entry for MMP platform
ARM: mmp/mmp2: fix cpu_is_mmp2() on mmp2-dt
MAINTAINERS: mediatek: Update SoC entry
ARM: dts: bcm2837: Fix polarity of wifi reset GPIOs
+ Linux 4.20-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/cpufreq/imx6q-cpufreq.c')
| -rw-r--r-- | drivers/cpufreq/imx6q-cpufreq.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index 8cfee0ab804b..d8c3595e9023 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -160,8 +160,13 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) /* Ensure the arm clock divider is what we expect */ ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); if (ret) { + int ret1; + dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); - regulator_set_voltage_tol(arm_reg, volt_old, 0); + ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); + if (ret1) + dev_warn(cpu_dev, + "failed to restore vddarm voltage: %d\n", ret1); return ret; } |