diff options
author | Andi Kleen <ak@linux.intel.com> | 2012-01-26 03:09:12 +0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2012-01-27 04:49:06 +0400 |
commit | fa8031aefec0cf7ea6c2387c93610d99d9659aa2 (patch) | |
tree | a174505948159296198a66874655868b78718bde /drivers/cpufreq/cpufreq-nforce2.c | |
parent | 2f1e097e24defe64a86535b53768f5c8ab0368d1 (diff) | |
download | linux-fa8031aefec0cf7ea6c2387c93610d99d9659aa2.tar.xz |
cpufreq: Add support for x86 cpuinfo auto loading v4
This marks all the x86 cpuinfo tables to the CPU specific device drivers,
to allow auto loading by udev. This should simplify the distribution
startup scripts for this greatly.
I didn't add MODULE_DEVICE_IDs to the centrino and p4-clockmod drivers,
because those probably shouldn't be auto loaded and the acpi driver
be used instead (not fully sure on that, would appreciate feedback)
The old nforce drivers autoload based on the PCI ID.
ACPI cpufreq is autoloaded in another patch.
v3: Autoload gx based on PCI IDs only. Remove cpu check (Dave Jones)
v4: Use newly introduce HW_PSTATE feature for powernow-k8 loading
Cc: Dave Jones <davej@redhat.com>
Cc: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Renninger <trenn@suse.de>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/cpufreq/cpufreq-nforce2.c')
-rw-r--r-- | drivers/cpufreq/cpufreq-nforce2.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/cpufreq/cpufreq-nforce2.c b/drivers/cpufreq/cpufreq-nforce2.c index 7bac808804f3..13d311ee08b3 100644 --- a/drivers/cpufreq/cpufreq-nforce2.c +++ b/drivers/cpufreq/cpufreq-nforce2.c @@ -385,6 +385,14 @@ static struct cpufreq_driver nforce2_driver = { .owner = THIS_MODULE, }; +#ifdef MODULE +static DEFINE_PCI_DEVICE_TABLE(nforce2_ids) = { + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 }, + {} +}; +MODULE_DEVICE_TABLE(pci, nforce2_ids); +#endif + /** * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic * |