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authorPaul Cercueil <paul@crapouillou.net>2018-06-27 15:14:59 +0300
committerStephen Boyd <sboyd@kernel.org>2018-07-06 21:47:28 +0300
commit2b555a4b9caecfcab1b2aade176df795ceceaefa (patch)
tree669673479270703249ca63368e52ea548a6eb7f6 /drivers/clk
parent574f4e80d59e5c669c0729718525df8bac5e4d78 (diff)
downloadlinux-2b555a4b9caecfcab1b2aade176df795ceceaefa.tar.xz
clk: ingenic: Add missing flag for UDC clock
The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/ingenic/jz4740-cgu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index bc073dd4470d..4479c102e899 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -161,7 +161,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
},
[JZ4740_CLK_UDC] = {
- "udc", CGU_CLK_MUX | CGU_CLK_DIV,
+ "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 29, 1 },
.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },