diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-05-05 05:31:55 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-12 23:48:43 +0300 |
| commit | dec396322d25ca5ce2f307b6da897060fdf9a782 (patch) | |
| tree | 19890695e2499f3b07a1e3a9b434a0cecc9e6bb7 /drivers/clk/tegra | |
| parent | 42329854410e672b7ffeb391d284ad719efcc465 (diff) | |
| download | linux-dec396322d25ca5ce2f307b6da897060fdf9a782.tar.xz | |
clk: tegra: Add Tegra210 CSI TPG clock gate
Tegra210 CSI hardware internally uses PLLD for internal test pattern
generator logic.
PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
out to CSI during TPG mode.
This patch adds this CSI TPG clock gate to Tegra210 clock driver
to allow Tegra video driver to ungate CSI TPG clock during TPG mode
and gate during non TPG mode.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index f2bb188fbc6a..68cbb98af567 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, |