diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-07-29 12:17:53 +0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-11-26 11:43:23 +0300 |
| commit | 4f4f85fa0b96a35429ebb4bc278d70ae0f72113c (patch) | |
| tree | 566618d20763f01c8a8b66fa1fe5f621373c4123 /drivers/clk/tegra/clk-tegra124.c | |
| parent | 7f06dd61248a75668bbb39b6fcca6ff407745df8 (diff) | |
| download | linux-4f4f85fa0b96a35429ebb4bc278d70ae0f72113c.tar.xz | |
clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.
Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra124.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index e3a85842ce0c..f5f9baca7bb6 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock); static DEFINE_SPINLOCK(pll_e_lock); static DEFINE_SPINLOCK(pll_re_lock); static DEFINE_SPINLOCK(pll_u_lock); +static DEFINE_SPINLOCK(emc_lock); /* possible OSC frequencies in Hz */ static unsigned long tegra124_input_freq[] = { @@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), 0, clk_base + CLK_SOURCE_EMC, - 29, 3, 0, NULL); + 29, 3, 0, &emc_lock); + + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + &emc_lock); + clks[TEGRA124_CLK_MC] = clk; /* cml0 */ clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, |