diff options
| author | Thierry Reding <treding@nvidia.com> | 2016-04-08 16:09:56 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 13:41:53 +0300 |
| commit | e8f6a68c508b5d1cc4612ada028d87c74ab279d5 (patch) | |
| tree | 47e8213aaf6ea3bf7286aa0eba891db80952824e /drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | |
| parent | 27ed2f7e7ca5c38a8ce695e58e6cf270c26f370b (diff) | |
| download | linux-e8f6a68c508b5d1cc4612ada028d87c74ab279d5.tar.xz | |
clk: tegra: dfll: Make code more comprehensible
Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra124-dfll-fcpu.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 6bfa5ca40d02..c7ffd4fd2231 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -47,7 +47,7 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, .speedo_scale = 100, .voltage_scale = 1000, - .cvb_table = { + .entries = { {204000000UL, {1112619, -29295, 402} }, {306000000UL, {1150460, -30585, 402} }, {408000000UL, {1190122, -31865, 402} }, @@ -107,11 +107,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -ENODEV; } - soc->cvb = tegra_cvb_build_opp_table(tegra124_cpu_cvb_tables, - ARRAY_SIZE(tegra124_cpu_cvb_tables), - process_id, speedo_id, speedo_value, - cpu_max_freq_table[speedo_id], - soc->dev); + soc->cvb = tegra_cvb_add_opp_table(soc->dev, tegra124_cpu_cvb_tables, + ARRAY_SIZE(tegra124_cpu_cvb_tables), + process_id, speedo_id, speedo_value, + cpu_max_freq_table[speedo_id]); if (IS_ERR(soc->cvb)) { dev_err(&pdev->dev, "couldn't add OPP table: %ld\n", PTR_ERR(soc->cvb)); |