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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-25 16:44:13 +0400 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 20:46:21 +0400 |
| commit | 8e9cc80aa348938078c3c1a7ab55efb3c40990e3 (patch) | |
| tree | 28f27ff2c2a39de09c0ec3a0f100b5c5243f0646 /drivers/clk/tegra/clk-tegra114.c | |
| parent | 04edb099a4a7e774a98b241dc016957922cbfb44 (diff) | |
| download | linux-8e9cc80aa348938078c3c1a7ab55efb3c40990e3.tar.xz | |
clk: tegra: use pll_ref as the pll_e parent
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index fa562e3e8f19..e62e4764131c 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -637,6 +637,7 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { /* PLLE special case: use cpcon field to store cml divider value */ {336000000, 100000000, 100, 21, 16, 11}, {312000000, 100000000, 200, 26, 24, 13}, + {12000000, 100000000, 200, 1, 24, 13}, {0, 0, 0, 0, 0, 0}, }; @@ -1301,7 +1302,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, clks[TEGRA114_CLK_PLL_RE_OUT] = clk; /* PLLE */ - clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", + clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref", clk_base, 0, 100000000, &pll_e_params, pll_e_freq_table, NULL); clk_register_clkdev(clk, "pll_e_out0", NULL); |