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| author | Herbert Xu <herbert@gondor.apana.org.au> | 2015-06-19 17:07:07 +0300 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2015-06-19 17:07:07 +0300 |
| commit | c0b59fafe31bf91f589736be304d739b13952fdd (patch) | |
| tree | 0088a41c6b68132739294643be06734e3af67677 /drivers/clk/tegra/clk-pll.c | |
| parent | 28bceeaaf81140d69647acd0eb7dc9312f27844a (diff) | |
| parent | bfa1ce5f38938cc9e6c7f2d1011f88eba2b9e2b2 (diff) | |
| download | linux-c0b59fafe31bf91f589736be304d739b13952fdd.tar.xz | |
Merge branch 'mvebu/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Merge the mvebu/drivers branch of the arm-soc tree which contains
just a single patch bfa1ce5f38938cc9e6c7f2d1011f88eba2b9e2b2 ("bus:
mvebu-mbus: add mv_mbus_dram_info_nooverlap()") that happens to be
a prerequisite of the new marvell/cesa crypto driver.
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index bfef9abdf232..05c6d08a6695 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -981,7 +981,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, struct tegra_clk_pll *pll = to_clk_pll(hw); struct tegra_clk_pll_freq_table cfg, old_cfg; unsigned long flags = 0; - int ret = 0; + int ret; ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); if (ret < 0) @@ -1005,7 +1005,7 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct tegra_clk_pll_freq_table cfg; - int ret = 0, p_div; + int ret, p_div; u64 output_rate = *prate; ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); @@ -1073,7 +1073,7 @@ static int clk_pllc_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); u32 val; - int ret = 0; + int ret; unsigned long flags = 0; if (pll->lock) @@ -1223,6 +1223,7 @@ static long _pllre_calc_rate(struct tegra_clk_pll *pll, return output_rate; } + static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { |