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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-04-03 18:40:40 +0400
committerStephen Warren <swarren@nvidia.com>2013-04-05 02:10:49 +0400
commit3e72771e210348fbd7ff0ea1b9e14cd88380c05b (patch)
tree5bb1543197683bdcaf8c8b4c5221147f717a7b6f /drivers/clk/tegra/clk-pll.c
parent0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f (diff)
downloadlinux-3e72771e210348fbd7ff0ea1b9e14cd88380c05b.tar.xz
clk: tegra: move from a lock bit idx to a lock mask
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
-rw-r--r--drivers/clk/tegra/clk-pll.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index ccb367ee7e78..0b963522479b 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -119,7 +119,7 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
{
int i;
- u32 val, lock_bit;
+ u32 val, lock_mask;
void __iomem *lock_addr;
if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
@@ -133,11 +133,11 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
else
lock_addr += pll->params->base_reg;
- lock_bit = BIT(pll->params->lock_bit_idx);
+ lock_mask = pll->params->lock_mask;
for (i = 0; i < pll->params->lock_delay; i++) {
val = readl_relaxed(lock_addr);
- if (val & lock_bit) {
+ if ((val & lock_mask) == lock_mask) {
udelay(PLL_POST_LOCK_DELAY);
return 0;
}