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| author | Jiancheng Xue <xuejiancheng@hisilicon.com> | 2016-04-23 10:40:30 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-06 21:13:32 +0300 |
| commit | 6c9da387c8d5c5254857d2782bd6c314226f4f27 (patch) | |
| tree | 3189ede959921db199f190d8aed8b8ab2fde692a /drivers/clk/sunxi/clk-a10-ve.c | |
| parent | f6ff57c8abde68c0bb8e0d4539f4204fc5ba45ae (diff) | |
| download | linux-6c9da387c8d5c5254857d2782bd6c314226f4f27.tar.xz | |
clk: hisilicon: add CRG driver for hi3519 soc
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/sunxi/clk-a10-ve.c')
0 files changed, 0 insertions, 0 deletions