diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-08 22:57:10 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-08 22:57:10 +0300 |
| commit | a063c1e120625a88bd63f0dc2534a62a58426e39 (patch) | |
| tree | b9606a77ef48f4288d29147f19be4bd0d0c6a9db /drivers/clk/sunxi/clk-a10-pll2.c | |
| parent | 67615c588a059b731df9d019edc3c561d8006ec9 (diff) | |
| parent | e4abe2b9ab3ac79537d99dfceff7302739a586bc (diff) | |
| download | linux-a063c1e120625a88bd63f0dc2534a62a58426e39.tar.xz | |
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: sunxi-ng: Fix wrong reset register offsets
clk: sunxi-ng: nk: Make ccu_nk_find_best static
clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
clk: sunxi: Fix return value check in sun8i_a23_mbus_setup()
clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
Diffstat (limited to 'drivers/clk/sunxi/clk-a10-pll2.c')
| -rw-r--r-- | drivers/clk/sunxi/clk-a10-pll2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c index 0ee1f363e4be..d8eab90ae661 100644 --- a/drivers/clk/sunxi/clk-a10-pll2.c +++ b/drivers/clk/sunxi/clk-a10-pll2.c @@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, SUN4I_PLL2_PRE_DIV_WIDTH, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, &sun4i_a10_pll2_lock); - if (!prediv_clk) { + if (IS_ERR(prediv_clk)) { pr_err("Couldn't register the prediv clock\n"); goto err_free_array; } @@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, &mult->hw, &clk_multiplier_ops, &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); - if (!base_clk) { + if (IS_ERR(base_clk)) { pr_err("Couldn't register the base multiplier clock\n"); goto err_free_multiplier; } |