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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-11-19 18:43:12 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-19 22:50:55 +0300 |
| commit | 8dc4af8bef127425271e06d09370a2479dae69c3 (patch) | |
| tree | 63114c00b05016b1744a70d8380db17e0e911087 /drivers/clk/st | |
| parent | 0bb4623f13d46b2ea054777accff0c41af8036be (diff) | |
| download | linux-8dc4af8bef127425271e06d09370a2479dae69c3.tar.xz | |
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/st')
0 files changed, 0 insertions, 0 deletions