diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-03-11 18:25:31 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2021-03-23 19:03:35 +0300 |
| commit | 3b218baa744b0c7161d1784414e0a9db6bc9bf6b (patch) | |
| tree | e46ded7ddb6ea0a979d0232449c0a69eae062ceb /drivers/clk/socfpga | |
| parent | fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8 (diff) | |
| download | linux-3b218baa744b0c7161d1784414e0a9db6bc9bf6b.tar.xz | |
clk: socfpga: allow building N5X clocks with ARCH_N5X
The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex
(ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor
changes. Also the clock drivers are the same.
However the clock drivers won't be build without ARCH_AGILEX. One could
assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not
modeled in Kconfig. In current stage the ARCH_N5X is simply
unbootable.
Add a separate Kconfig entry for clocks used by both ARCH_N5X and
ARCH_AGILEX so the necessary objects will be built if either of them is
selected.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga')
| -rw-r--r-- | drivers/clk/socfpga/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/clk/socfpga/Makefile | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig new file mode 100644 index 000000000000..3c30617169bf --- /dev/null +++ b/drivers/clk/socfpga/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +config CLK_INTEL_SOCFPGA64 + bool + # Intel Agilex / N5X clock controller support + default (ARCH_AGILEX || ARCH_N5X) + depends on ARCH_AGILEX || ARCH_N5X diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index bf736f8d201a..c6db8dd4ab35 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -3,5 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o -obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o +obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o |