diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2020-06-16 23:24:16 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-06-20 05:27:33 +0300 |
| commit | 6f3bcf56f8eec78e51cac8b3dd67ed7ec67e3e1e (patch) | |
| tree | 7e02a1d5cc0ae6366ef68bbc4c75d8f0d2d14842 /drivers/clk/socfpga/clk-agilex.c | |
| parent | c2710fdf935bb1286e8eb6a6b44991bab1fe87af (diff) | |
| download | linux-6f3bcf56f8eec78e51cac8b3dd67ed7ec67e3e1e.tar.xz | |
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-agilex.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-agilex.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 699527f7e764..1b2e0ad01b24 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -294,8 +294,12 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 8, 0, 0, 0, 0, 0, 0}, { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9, 0, 0, 0, 0, 0, 0}, - { AGILEX_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0x7C, + { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 10, 0, 0, 0, 0, 0, 0}, + { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C, + 10, 0, 0, 0, 0, 0, 4}, + { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C, + 10, 0, 0, 0, 0, 0, 4}, }; static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, |