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authorTomasz Figa <t.figa@samsung.com>2013-12-21 02:58:38 +0400
committerKukjin Kim <kgene.kim@samsung.com>2013-12-21 02:58:38 +0400
commit86576fbe201b7617e9dc689df0e5df0807acdd30 (patch)
treec24f9da39e2d6f9a61bd070a87b4fd0bf238c508 /drivers/clk/samsung
parenta98e3190fc7dbb6157ef51ce8d92a36b06d282bb (diff)
downloadlinux-86576fbe201b7617e9dc689df0e5df0807acdd30.tar.xz
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ad5ff50c5f28..d967571d305e 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
- DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
+ DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),