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| author | Michael Turquette <mturquette@baylibre.com> | 2015-12-22 21:12:42 +0300 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2015-12-22 22:57:33 +0300 |
| commit | eaaa6fb53f2652760c1c512534fe3e71672a7d78 (patch) | |
| tree | 7d132f3caec6b261f1d86df212962eaabcf59874 /drivers/clk/rockchip/clk-rk3188.c | |
| parent | d90e149666258bc84e14c1c31c2064a345220cd7 (diff) | |
| parent | dfff24bde7fb8d57482e907d5dfb0be3a9e28119 (diff) | |
| download | linux-eaaa6fb53f2652760c1c512534fe3e71672a7d78.tar.xz | |
Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3188.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index abb47608713b..c2c35d4cdda8 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -750,7 +750,7 @@ static void __init rk3188_common_clk_init(struct device_node *np) rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); - rockchip_register_restart_notifier(RK2928_GLB_SRST_FST); + rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); } static void __init rk3066a_clk_init(struct device_node *np) |