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| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-03-09 05:37:03 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-03-27 14:03:33 +0300 |
| commit | 268aebaa2410152bf91ea1ede6b284ff8138822d (patch) | |
| tree | f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0 /drivers/clk/rockchip/clk-pll.c | |
| parent | 9387bfd19b457085189d918ef117ffd63c4d67a0 (diff) | |
| download | linux-268aebaa2410152bf91ea1ede6b284ff8138822d.tar.xz | |
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-pll.c')
0 files changed, 0 insertions, 0 deletions