diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-08-30 16:45:15 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-10-21 10:53:54 +0300 |
| commit | 362c79f75c9ff129935d30279812a0d9c63eb76b (patch) | |
| tree | 68322eacf493afbfd870a60691ab380eda54e319 /drivers/clk/renesas | |
| parent | df98719f033cf5903febf036ffdeb5b0f77a0fda (diff) | |
| download | linux-362c79f75c9ff129935d30279812a0d9c63eb76b.tar.xz | |
clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long. Hence switch the SD clocks on R-Car Gen3 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.
This includes implementing range checking.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190830134515.11925-9-geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 4c2821afd365..c97b647db9b6 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -315,8 +315,8 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, clock->div_table[clock->cur_div_idx].div); } -static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_sd_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX; struct sd_clock *clock = to_sd_clock(hw); @@ -324,19 +324,24 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; for (i = 0; i < clock->div_num; i++) { - calc_rate = DIV_ROUND_CLOSEST(*parent_rate, + calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, clock->div_table[i].div); - diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; + if (calc_rate < req->min_rate || calc_rate > req->max_rate) + continue; + + diff = calc_rate > req->rate ? calc_rate - req->rate + : req->rate - calc_rate; if (diff < diff_min) { best_rate = calc_rate; diff_min = diff; } } - if (best_rate > LONG_MAX) + if (best_rate == ULONG_MAX) return -EINVAL; - return best_rate; + req->rate = best_rate; + return 0; } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, @@ -367,7 +372,7 @@ static const struct clk_ops cpg_sd_clock_ops = { .disable = cpg_sd_clock_disable, .is_enabled = cpg_sd_clock_is_enabled, .recalc_rate = cpg_sd_clock_recalc_rate, - .round_rate = cpg_sd_clock_round_rate, + .determine_rate = cpg_sd_clock_determine_rate, .set_rate = cpg_sd_clock_set_rate, }; |