diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2020-12-18 20:37:27 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-12-28 12:52:58 +0300 |
| commit | ab2ccacd73867c6be285ba4f3c1a3e10b96e9a1d (patch) | |
| tree | fa5894208ffec1be91892bd0977cbc306a4eccda /drivers/clk/renesas | |
| parent | 57be2dc8d4cf4791993bd3e4caf586f3adfb7f6d (diff) | |
| download | linux-ab2ccacd73867c6be285ba4f3c1a3e10b96e9a1d.tar.xz | |
clk: renesas: r8a779a0: Add RWDT clocks
And introduce critical clocks, too, because RWDT is one.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201218173731.12839-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index d7825adcb19d..f93ba9a6cb26 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -192,6 +192,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1), DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), + DEF_MOD("rwdt", 907, R8A779A0_CLK_R), DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), @@ -269,6 +270,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, __clk_get_name(parent), 0, mult, div); } +static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { + MOD_CLK_ID(907), /* RWDT */ +}; + /* * CPG Clock Data */ @@ -319,6 +324,10 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), .num_hw_mod_clks = 15 * 32, + /* Critical Module Clocks */ + .crit_mod_clks = r8a779a0_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks), + /* Callbacks */ .init = r8a779a0_cpg_mssr_init, .cpg_clk_register = rcar_r8a779a0_cpg_clk_register, |