diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-09-22 18:51:43 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-24 16:11:05 +0300 |
| commit | 70a4af3662e073768a68a7ed5a82f49677cbde0c (patch) | |
| tree | 0eb086f73beb58388ab1de4abd82f4caeeb1ef17 /drivers/clk/renesas/rzg2l-cpg.h | |
| parent | 7c5a2561737d88b55764034b27f897498e90a319 (diff) | |
| download | linux-70a4af3662e073768a68a7ed5a82f49677cbde0c.tar.xz | |
clk: renesas: r9a07g044: Add ethernet clock sources
Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.
This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match
with the register description as mentioned in RZ/G2L HW manual (Rev.1.00).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rzg2l-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index f538ffa3371c..5202c0512483 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -11,6 +11,7 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL6_ETH_SSEL (0x418) /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) @@ -27,6 +28,8 @@ #define SEL_PLL_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) +#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) + /** * Definitions of CPG Core Clocks * |