diff options
author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-29 08:38:56 +0300 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 14:45:22 +0300 |
commit | 3e8008fcf6b7f7c65ad2718c18fb79f37007f1a5 (patch) | |
tree | fc69bc41a6b87808ed45f4805736535950c7d594 /drivers/clk/renesas/r9a07g044-cpg.c | |
parent | 97c1c4ccda76d2919775d748cf223637cf0e82ae (diff) | |
download | linux-3e8008fcf6b7f7c65ad2718c18fb79f37007f1a5.tar.xz |
clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
Remove CPG_SDHI_DSEL and its bits from the generic header as RZ/G3S has
different offset registers and bits for this, thus avoid mixing them.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-10-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r9a07g044-cpg.c')
-rw-r--r-- | drivers/clk/renesas/r9a07g044-cpg.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index c597414a94d8..d4dcf5d896d4 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -15,6 +15,13 @@ #include "rzg2l-cpg.h" +/* Specific registers. */ +#define CPG_PL2SDHI_DSEL (0x218) + +/* Clock select configuration. */ +#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, |