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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-29 18:22:44 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-05-15 10:46:31 +0300 |
| commit | b7c563c489e94417efbad68d057ea5d2030ae44c (patch) | |
| tree | 4347081c672443bfaa6d76c8dafb55daab9a7359 /drivers/clk/renesas/r8a7745-cpg-mssr.c | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff) | |
| download | linux-b7c563c489e94417efbad68d057ea5d2030ae44c.tar.xz | |
clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.
This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.
Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7745-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions