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authorStephen Boyd <sboyd@codeaurora.org>2016-11-10 04:08:28 +0300
committerStephen Boyd <sboyd@codeaurora.org>2016-11-10 04:10:32 +0300
commitcbf2e548ca8ad4bb274d014e9a70bd841d29948e (patch)
tree2a96bb0a385ea5cae53c845266b9f2f989989fa2 /drivers/clk/qcom
parent84558ff77067e761e9e1bc70fff79079c12d5ac9 (diff)
downloadlinux-cbf2e548ca8ad4bb274d014e9a70bd841d29948e.tar.xz
clk: qcom: ipq806x: Fix board clk rates
The clocks on these boards run at 25 MHz, not 19.2 and 27 like other platforms. Unfortunately I copy/pasted from other similar SoCs but forgot this one is different. Fix it. Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom')
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 52a7d3959875..28eb200d0f1e 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -2990,11 +2990,11 @@ static int gcc_ipq806x_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
+ ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
if (ret)
return ret;
- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
+ ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
if (ret)
return ret;