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author | Stephen Boyd <sboyd@codeaurora.org> | 2018-01-27 03:41:39 +0300 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2018-01-27 03:41:39 +0300 |
commit | 74b48999b1c80f42ad0477341aac7249d2641b04 (patch) | |
tree | 9cf796b7c540e31be7f377690c683eaeef47a63c /drivers/clk/qcom | |
parent | 90552a6f9312861ff2481fc9802c4cf6be02e338 (diff) | |
parent | 23c68cc9683efbd08457f06fb5eacd7c8616dfae (diff) | |
parent | 29fd2a34ef8d863e48183bd473ba57c8d7839e25 (diff) | |
parent | 6562fbcf3ad5ffa56f1fc79bb1afae909cf3627b (diff) | |
parent | 7956a0319eadbb53c8f2cd7e689f99445636ebf2 (diff) | |
download | linux-74b48999b1c80f42ad0477341aac7249d2641b04.tar.xz |
Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' and 'clk-omap' into clk-next
* clk-qcom-alpha-pll:
clk: qcom: add read-only alpha pll post divider operations
clk: qcom: support for 2 bit PLL post divider
clk: qcom: support Brammo type Alpha PLL
clk: qcom: support Huayra type Alpha PLL
clk: qcom: support for dynamic updating the PLL
clk: qcom: support for alpha mode configuration
clk: qcom: flag for 64 bit CONFIG_CTL
clk: qcom: fix 16 bit alpha support calculation
clk: qcom: support for alpha pll properties
* clk-check-ops-ptr:
clk: check ops pointer on clock register
* clk-protect-rate:
clk: fix set_rate_range when current rate is out of range
clk: add clk_rate_exclusive api
clk: cosmetic changes to clk_summary debugfs entry
clk: add clock protection mechanism to clk core
clk: use round rate to bail out early in set_rate
clk: rework calls to round and determine rate callbacks
clk: add clk_core_set_phase_nolock function
clk: take the prepare lock out of clk_core_set_parent
clk: fix incorrect usage of ENOSYS
* clk-omap:
clk: ti: Drop legacy clk-3xxx-legacy code