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authorStephen Boyd <sboyd@kernel.org>2024-03-13 22:36:21 +0300
committerStephen Boyd <sboyd@kernel.org>2024-03-13 22:36:21 +0300
commit3066c521be9db14964d78c6c431c97a424468ded (patch)
tree8ce47ec16eaa655f1a4e53c8643aca48be5b15e9 /drivers/clk/qcom/dispcc-x1e80100.c
parent68e4ebd542f34c1b87eee725ca941484d941cf38 (diff)
parentd289ca74e96afad6d1815d9218d40e867feeef3d (diff)
parent79b92ba0ef73d7c33876abb2a5e71276f20afbd1 (diff)
parent3e76237ee7cfb6f74e9a82d45a85a90e7ee64ae5 (diff)
parent99f4570cfba1e60daafde737cb7e395006d719e6 (diff)
parentb0cde62e4c548b2e7cb535caa6eb0df135888601 (diff)
downloadlinux-3066c521be9db14964d78c6c431c97a424468ded.tar.xz
Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next
- Increase dev_id len for clkdev lookups * clk-samsung: (25 commits) clk: samsung: Add CPU clock support for Exynos850 clk: samsung: Pass mask to wait_until_mux_stable() clk: samsung: Keep register offsets in chip specific structure clk: samsung: Keep CPU clock chip specific data in a dedicated struct clk: samsung: Pass register layout type explicitly to CLK_CPU() clk: samsung: Pass actual CPU clock registers base to CPU_CLK() clk: samsung: Group CPU clock functions by chip clk: samsung: Use single CPU clock notifier callback for all chips clk: samsung: Reduce params count in exynos_register_cpu_clock() clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c clk: samsung: Improve clk-cpu.c style dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 clk: samsung: gs101: add support for cmu_peric1 clk: samsung: gs101: drop extra empty line dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit clk: samsung: exynos850: Propagate SPI IPCLK rate change clk: samsung: gs101: gpio_peric0_pclk needs to be kept on clk: samsung: exynos850: Add PDMA clocks dt-bindings: clock: tesla,fsd: Fix spelling mistake clk: samsung: gs101: add support for cmu_peric0 ... * clk-imx: clk: imx: imx8mp: Fix SAI_MCLK_SEL definition clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev() clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite() clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection * clk-rockchip: clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent clk: rockchip: rk3588: use linked clock ID for GATE_LINK clk: rockchip: rk3588: fix indent clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf dt-bindings: clock: rk3588: add missing PCLK_VO1GRF dt-bindings: clock: rk3588: drop CLK_NR_CLKS clk: rockchip: rk3588: fix CLK_NR_CLKS usage clk: rockchip: rk3568: Add PLL rate for 128MHz * clk-clkdev: clkdev: Update clkdev id usage to allow for longer names * clk-rate-exclusive: clk: Add a devm variant of clk_rate_exclusive_get()