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authorJerome Brunet <jbrunet@baylibre.com>2017-12-21 19:30:54 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-04-12 13:32:13 +0300
commite6bc3a4b0c23ed8d754692fa15ceb280e3facc51 (patch)
treecf15b8c5fba5ddf59f7e98eafbf1162b548a65d9 /drivers/clk/qcom/clk-regmap-divider.c
parent1cf98fd005f54f480aba21f1d73a0059f460a353 (diff)
downloadlinux-e6bc3a4b0c23ed8d754692fa15ceb280e3facc51.tar.xz
clk: divider: fix incorrect usage of container_of
[ Upstream commit 12a26c298d2a8b1cab498533fa65198e49e3afd3 ] divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clk/qcom/clk-regmap-divider.c')
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
index 53484912301e..928fcc16ee27 100644
--- a/drivers/clk/qcom/clk-regmap-divider.c
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -59,7 +59,7 @@ static unsigned long div_recalc_rate(struct clk_hw *hw,
div &= BIT(divider->width) - 1;
return divider_recalc_rate(hw, parent_rate, div, NULL,
- CLK_DIVIDER_ROUND_CLOSEST);
+ CLK_DIVIDER_ROUND_CLOSEST, divider->width);
}
const struct clk_ops clk_regmap_div_ops = {