diff options
| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-09-28 20:50:44 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-14 00:45:33 +0300 |
| commit | c45ae598fc16aca8ca8778a9b85e41449e8e5182 (patch) | |
| tree | 827f41fc26453761613fa98041d999f10b5fc0c4 /drivers/clk/qcom/clk-alpha-pll.c | |
| parent | 26945e0a2341523170aa5b6ff4cc35e9ce1f7cf4 (diff) | |
| download | linux-c45ae598fc16aca8ca8778a9b85e41449e8e5182.tar.xz | |
clk: qcom: support for alpha mode configuration
The current configuration does not fully configure PLL alpha mode
and values so this patch
1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha.
2. Adds alpha enable and alpha mode configuration support.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 81cfd31f569a..38ed1b83a094 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -143,6 +143,9 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_write(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + if (pll_alpha_width(pll) > 32) + regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); + val = config->main_output_mask; val |= config->aux_output_mask; val |= config->aux2_output_mask; @@ -150,6 +153,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, val |= config->pre_div_val; val |= config->post_div_val; val |= config->vco_val; + val |= config->alpha_en_mask; + val |= config->alpha_mode_mask; mask = config->main_output_mask; mask |= config->aux_output_mask; |