diff options
| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-09-28 20:50:43 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-14 00:45:32 +0300 |
| commit | 26945e0a2341523170aa5b6ff4cc35e9ce1f7cf4 (patch) | |
| tree | 2be3f77a1a0809f4e9b7c21345848f444d30c871 /drivers/clk/qcom/clk-alpha-pll.c | |
| parent | 1e859d3e03f0ac97d15e1952bddda4b29de1c71c (diff) | |
| download | linux-26945e0a2341523170aa5b6ff4cc35e9ce1f7cf4.tar.xz | |
clk: qcom: flag for 64 bit CONFIG_CTL
Some of the Alpha PLLs (like Spark and Brammo) don't have a
CONFIG_CTL_U register. Add logic to detect when PLLs don't have
this second config register and skip programming it during PLL
initialization.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 3890f20be7d5..81cfd31f569a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -82,6 +82,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) +#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) + #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ struct clk_alpha_pll, clkr) @@ -136,7 +138,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, regmap_write(regmap, PLL_L_VAL(pll), config->l); regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); - regmap_write(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); + + if (pll_has_64bit_config(pll)) + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), + config->config_ctl_hi_val); val = config->main_output_mask; val |= config->aux_output_mask; |