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authorStephen Boyd <sboyd@codeaurora.org>2018-08-14 15:12:22 +0300
committerStephen Boyd <sboyd@kernel.org>2018-10-17 23:14:40 +0300
commitcb546b797a0da4dbb1a0c76a2a357921887b6189 (patch)
treea7953166a78f10ad5e9cd351c4faf58dc15cb9b2 /drivers/clk/qcom/Kconfig
parentb3f2f10693aadeacf83ab5be03810941a4b77612 (diff)
downloadlinux-cb546b797a0da4dbb1a0c76a2a357921887b6189.tar.xz
clk: qcom: Add HFPLL driver
On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/Kconfig')
-rw-r--r--drivers/clk/qcom/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 064768699fe7..21aec1048225 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV
Technologies, Inc. SPMI PMIC. It configures the frequency of
clkdiv outputs of the PMIC. These clocks are typically wired
through alternate functions on GPIO pins.
+
+config QCOM_HFPLL
+ tristate "High-Frequency PLL (HFPLL) Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the high-frequency PLLs present on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling on devices
+ such as MSM8974, APQ8084, etc.