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| author | Samuel Holland <samuel@sholland.org> | 2019-12-29 05:59:22 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-01-02 12:28:47 +0300 |
| commit | 0c545240aebc2ccb8f661dc54283a14d64659804 (patch) | |
| tree | d750a31730f12d9a50b1db022b4adfec6b1688e2 /drivers/clk/pistachio | |
| parent | 675a6d467b432c8b4a0703ded02e6ef068e0c7e9 (diff) | |
| download | linux-0c545240aebc2ccb8f661dc54283a14d64659804.tar.xz | |
clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order
According to the BSP source code, both the AR100 and R_APB2 clocks have
PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre-
divider used for PLL_PERIPH0 should be changed to index 3 to match.
This was verified by running a rough benchmark on the AR100 with various
clock settings:
| mux | pre-divider | iterations/second | clock source |
|=====|=============|===================|==============|
| 0 | 0 | 19033 (stable) | osc24M |
| 2 | 5 | 11466 (unstable) | iosc/osc16M |
| 2 | 17 | 11422 (unstable) | iosc/osc16M |
| 3 | 5 | 85338 (stable) | pll-periph0 |
| 3 | 17 | 27167 (stable) | pll-periph0 |
The relative performance numbers all match up (with pll-periph0 running
at its default 600MHz).
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/clk/pistachio')
0 files changed, 0 insertions, 0 deletions